1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor package, and more particularly, to a method for manufacturing a semiconductor package solidly bonding a cap substrate and a device substrate having different thermal expansion coefficients through two times of bonding.
2. Description of the Related Art
A semiconductor package forms a circuit unit on a device substrate and covers a cap substrate having an external electrode and a through electrode electrically connected with the circuit unit to protect the circuit unit.
The semiconductor package is used for a surface acoustic wave (SAW) filter having an interdigital transducer (IDT) electrode which is sensitive to the influence of an external environment and thus requires blocking from the external environment, or an image sensor having an image forming region. These parts are manufactured at a wafer level for miniaturization.
Examples of a related art regarding a method of manufacturing the semiconductor package include U.S. Pat. No. 5,448,014 and Japanese Laid Open Patent No. 2004-366879.
However, since the method for manufacturing the semiconductor package passes through a process of bonding at high temperature, bonding is twisted or crack is generated in the case where the device substrate and the cap substrate have different thermal expansion coefficients. Accordingly, there is a limitation of having to manufacture the device substrate and the cap substrate using only the same material or materials having similar thermal expansion properties. Accordingly, even a material of the cap substrate merely covering the device substrate to protect or seal a circuit unit such as an IDT electrode provided inside the cap substrate should be manufactured using the same material as that of an expensive device substrate. Therefore, there has been a limit in cost reduction and a process required for dealing with the expensive substrate is complicated.